(untitled) (Global Journals of Research in Engineering, 2022)
In this article, we present the multichannel architecture of the analog-to-digital converter based on the duty cycle modulation technique with prototyping on FPGA hardware targets. This diagram is the continuation of the work presented in [1],[2] proving the feasibility of the single-channel version of this converter on the one hand and its characterization on the other. This conversion approach is based on the use of parallel duty cycle modulation cells, each used as an independent 1-bit interfacing circuit per analog channel. In addition, all of the modulated output bits associated with all of the analog inputs are simultaneously sampled and processed. The principle already demonstrated [11] and the important properties revealed by this A / D conversion scheme studied in depth in the review articles are presented, then, an experiment with a 4-channel virtual oscilloscope is presented, in order to show the potential results of the prototype of the multi-channel version of the FPGA-based converter. The design and implementation are carried out by software and hardware co-simulation using platforms such as the Simulink / Xilinx based system generators in which the ODCM-ADC is implemented, and the programming tool Vivado 2019.2 from Xilinx. The hardware platform consists of the Zynq 7000 FPGA kit (25 MHz sample clock), equipped with an integrated FPGA-based IIR (infinite impulse response) digital decimation filter and a JTAG communication cable / connectors on PC. The co-simulation systems are built and successfully tested for a modulating bandwidth of 3 KHz. These performance levels, obtained under virtual and hardware co-simulation conditions, show a relevant challenge of an oversampling multichannel ADC, compared to most ADC oversampling techniques. As a merit, the proposed FPGA-based ADC technique is a novel and relevant ADC architecture for on-board instrumentation systems and industrial electronics.