Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art (Global Journals of Research in Engineering, 2013)
Testing time, power dissipation and others are major challenging optimization problems while testing digital circuits and VLSI circuits. Unluckily, most of these problems are frequently solved by heuristic ways which do not assure best solution. The analysis of situation of art models and answers in such optimization problems were carried out in this paper, especially for power optimization in digital VLSI circuit testing.
Keywords: very large scale integration (VLSI); inte-grated circuit(ic); low power testing; bist; ate; scan test