Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Authors

  • Y. Sreenivasula Goud

  • Dr.B.K.Madhavi

Keywords:

very large scale integration (VLSI), inte-grated circuit(ic), low power testing, bist, ate, scan test

Abstract

Testing time, power dissipation and others are major challenging optimization problems while testing digital circuits and VLSI circuits. Unluckily, most of these problems are frequently solved by heuristic ways which do not assure best solution. The analysis of situation of art models and answers in such optimization problems were carried out in this paper, especially for power optimization in digital VLSI circuit testing.

Downloads

How to Cite

Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art. (2013). Global Journals of Research in Engineering, 13(F7), 13-31. https://testing.engineeringresearch.org/index.php/GJRE/article/view/791

 
Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art

Published

2013-05-15

Issue

Vol. 13 No. F7 (2013): GJRE-F Electrical and Electronic: Volume 13 Issue F7

Section

Articles

License

Copyright (c) 2013 Authors and Global Journals Private Limited

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art. (2013). Global Journals of Research in Engineering, 13(F7), 13-31. https://testing.engineeringresearch.org/index.php/GJRE/article/view/791